CVE-2025-0647
In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
Scoring
- CVSS base score
- 0
- EPSS probability
- 0.16%
- CWE
- CWE-226
- Published
- 2026-01-14
- Last modified
- 2026-03-13
Affected products
- Arm Neoverse-N2
- Arm Neoverse-V3AE
- Arm Neoverse-V3
- Arm Neoverse-V2
- Arm Cortex-X925
- Arm Cortex-X4
- Arm Cortex-X3
- Arm Cortex-X2
Weakness type
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