# CVE-2025-0647

## Summary

- **CVE ID:** CVE-2025-0647
- **Severity:** UNKNOWN
- **CVSS Score:** 0
- **CWE:** CWE-226
- **Published:** Jan 14, 2026
- **Last Modified:** Mar 13, 2026

## Description

In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.

## Affected Products

- Arm — Neoverse-N2 (0)
- Arm — Neoverse-V3AE (0)
- Arm — Neoverse-V3 (0)
- Arm — Neoverse-V2 (0)
- Arm — Cortex-X925 (0)
- Arm — Cortex-X4 (0)
- Arm — Cortex-X3 (0)
- Arm — Cortex-X2 (0)
- Arm — Cortex-A710 (0)
- Arm — C1-Premium (0)
- Arm — C1-Ultra (0)

## References

- [CNA](https://developer.arm.com/documentation/111546)
- [CISA-ADP](https://graph.volerion.com/view?ID=CVE-2025-0647)

## Exploitation Prediction (EPSS)

- **EPSS Score:** 0.16%
- **EPSS Percentile:** 5.4

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_Exported from OnDuty AI Vulnerability Intelligence on 2026-09-10._