CWE-1421: Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.
4 tracked CVEs are classified under this weakness.
Highest-risk vulnerabilities
- CVE-2024-38296 — Dell Edge Gateway 3200, versions prior to 15.40.30.2879, and Edge Gateway 5200, versions prior to 12.0.94.2380, contain
- CVE-2024-36357 — A transient execution vulnerability in some AMD processors may allow an attacker to infer data in the L1D cache, potenti
- CVE-2024-36350 — A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, pot
- CVE-2024-28956 — Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) P
Recently published
- CVE-2024-36357 — A transient execution vulnerability in some AMD processors may allow an attacker to infer data in the L1D cache, potenti
- CVE-2024-36350 — A transient execution vulnerability in some AMD processors may allow an attacker to infer data from previous stores, pot
- CVE-2024-28956 — Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) P
- CVE-2024-38296 — Dell Edge Gateway 3200, versions prior to 15.40.30.2879, and Edge Gateway 5200, versions prior to 12.0.94.2380, contain